Increase width of power bus, just in case.

This commit is contained in:
Anna Rose 2021-11-19 19:15:53 -05:00
parent 99f9ad3613
commit 28c135140c

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@ -1108,11 +1108,11 @@ design rules under a new name.</description>
<signal name="VCC">
<contactref element="ARDUINO" pad="5V"/>
<contactref element="MUX" pad="18"/>
<wire x1="20.32" y1="30.48" x2="22.606" y2="30.48" width="0.1524" layer="16"/>
<wire x1="20.32" y1="30.48" x2="19.05" y2="29.21" width="0.1524" layer="16"/>
<wire x1="19.05" y1="29.21" x2="19.05" y2="17.78" width="0.1524" layer="16"/>
<wire x1="19.05" y1="17.78" x2="16.637" y2="17.78" width="0.1524" layer="16"/>
<wire x1="22.606" y1="30.48" x2="23.876" y2="31.75" width="0.1524" layer="16"/>
<wire x1="22.606" y1="30.48" x2="20.32" y2="30.48" width="0.6096" layer="16"/>
<wire x1="20.32" y1="30.48" x2="19.05" y2="29.21" width="0.6096" layer="16"/>
<wire x1="19.05" y1="29.21" x2="19.05" y2="17.78" width="0.6096" layer="16"/>
<wire x1="19.05" y1="17.78" x2="16.637" y2="17.78" width="0.6096" layer="16"/>
<wire x1="22.606" y1="30.48" x2="23.876" y2="31.75" width="0.6096" layer="16"/>
</signal>
<signal name="N$24">
<contactref element="MUX" pad="14"/>